The invention relates to a multiple redundant clock system, comprising a number of n.gtoreq.4 mutually synchronizing clocks, each of which comprises a respective clock output for a bivalent clock signal, system comprising an interconnection network for applying the clock signal of each clock to each of the other clocks, each clock comprising an oscillator circuit and a deviation-determining device to an input of which the oscillator circuit is connected via an interconnection and which comprises further inputs for receiving the clock signals of the other clocks. A clock system of this kind is known from U.S. Pat. No. 4,239,982 to T. Basil Smith et al. which is incorporated herein by way of reference. Such a clock system is used, for example, in a digital device which is composed of a number of stations which must operate in synchronism, for example in a multiprocessor computer system in which each processor comprises its own clock. The number n of processors provides a system redundancy so that a correctly operating system is obtained even with a smaller number of correctly operating processors, for example (n-1). There are also other applications for such a clock system. In such known system a desynchronized state of one of the clocks is indicated, while the other clocks of the system can continue in a mutually synchronized state.